A general-purpose model translation system for a universal neural chip
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: theory and algorithms - Volume Part I
A combined arithmetic logic unit and memory element for the design of a parallel computer
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
A hierachical configuration system for a massively parallel neural hardware platform
Proceedings of the 9th conference on Computing Frontiers
Scalable communications for a million-core neural processing architecture
Journal of Parallel and Distributed Computing
A real-time, event-driven neuromorphic system for goal-directed attentional selection
ICONIP'12 Proceedings of the 19th international conference on Neural Information Processing - Volume Part II
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
Neural Processing Letters
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The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support large-scale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the develop-ment has resulted in innovation at every level of design, including a self-timed inter-chip communic-ation system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation.