Neural networks for pattern recognition
Neural networks for pattern recognition
Fast sigmoidal networks via spiking neurons
Neural Computation
Networks of spiking neurons: the third generation of neural network models
Transactions of the Society for Computer Simulation International - Special issue: simulation methodology in transportation systems
Communicating neuronal ensembles between neuromorphic chips
Neuromorphic systems engineering
Computers and Intractability: A Guide to the Theory of NP-Completeness
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Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Polychronization: Computation with Spikes
Neural Computation
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
IEEE Transactions on Computers
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
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Proceedings of the 23rd international conference on Supercomputing
A Programmable Adaptive Router for a GALS Parallel System
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
The Deferred Event Model for Hardware-Oriented Spiking Neural Networks
Advances in Neuro-Information Processing
The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Proceedings of the 7th ACM international conference on Computing frontiers
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker
Proceedings of the 7th ACM international conference on Computing frontiers
A general-purpose model translation system for a universal neural chip
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: theory and algorithms - Volume Part I
A real-time, FPGA based, biologically plausible neural network processor
ICANN'05 Proceedings of the 15th international conference on Artificial neural networks: formal models and their applications - Volume Part II
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.