Design of low-cost, real-time simulation systems for large neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
GENES IV: a bit-serial processing element for a multi-model neural-network accelerator
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Special-purpose digital hardware for neural networks: an architectural survey
Journal of VLSI Signal Processing Systems
Relation between retinotopical and orientation maps in visual cortex
Neural Computation
VLSI Implementation of a Neural Model Using Spikes
Analog Integrated Circuits and Signal Processing
Neuromorphic Synapses for Artificial Dendrites
Analog Integrated Circuits and Signal Processing
Simulation of Spiking Neural Networks on Different Hardware Platforms
ICANN '97 Proceedings of the 7th International Conference on Artificial Neural Networks
Using GPUs for Machine Learning Algorithms
ICDAR '05 Proceedings of the Eighth International Conference on Document Analysis and Recognition
Towards cortex sized artificial neural systems
Neural Networks
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation
HIS '07 Proceedings of the 7th International Conference on Hybrid Intelligent Systems
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
Anatomy of a cortical simulator
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
A universal abstract-time platform for real-time neural networks
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture
The Computer Journal
Proceedings of the 7th ACM international conference on Computing frontiers
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system
Proceedings of the 7th ACM international conference on Computing frontiers
The role of chaotic resonance in cerebellar learning
Neural Networks
A general-purpose model translation system for a universal neural chip
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: theory and algorithms - Volume Part I
Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign
IEEE Transactions on Neural Networks
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
Silicon auditory processors as computer peripherals
IEEE Transactions on Neural Networks
Scalable communications for a million-core neural processing architecture
Journal of Parallel and Distributed Computing
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Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience.