Digital simulation of spiking neural networks
Pulsed neural networks
Antidromic Spikes Drive Hebbian Learning in an Artificial Dendritic Tree
Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon
SystemC: a modeling platform supporting multiple design abstractions
Proceedings of the 14th international symposium on Systems synthesis
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks
Proceedings of the conference on Design, automation and test in Europe - Volume 3
ARM System Developer's Guide: Designing and Optimizing System Software
ARM System Developer's Guide: Designing and Optimizing System Software
Towards cortex sized artificial neural systems
Neural Networks
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
SpiNNaker: The Design Automation Problem
Advances in Neuro-Information Processing
The Deferred Event Model for Hardware-Oriented Spiking Neural Networks
Advances in Neuro-Information Processing
A hardware/software framework for real-time spiking systems
ICANN'05 Proceedings of the 15th international conference on Artificial Neural Networks: biological Inspirations - Volume Part I
Synaptic plasticity in spiking neural networks (SP2INN): a system approach
IEEE Transactions on Neural Networks
Simple model of spiking neurons
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system
Proceedings of the 7th ACM international conference on Computing frontiers
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High-speed asynchronous hardware makes it possible to virtualise neural networks' temporal dynamics as well as their structure. Through SpiNNaker, a dedicated neural chip multiprocessor, we introduce a real-time modelling architecture that makes the neural model run on the device independent of the hardware specifics. The central features of this modelling architecture are : native concurrency, ability to support very large (≫ 109 neurons) networks, and decoupling of the temporal and spatial characteristics of the model from those of the hardware. It circumvents a virtually fatal tradeoff in large-scale neural hardware between model support limitations or scalability limitations, without imposing a synchronous timing model. The chip itself combines an array of general-purpose processors with a configurable asynchronous interconnect and memory fabric to achieve true on- and off-chip parallelism, universal network architecture support, and programmable temporal dynamics. An HDL-like concurrent configuration software model using libraries of templates, allows the user to embed the neural model onto the hardware, mapping the virtual network structure and time dynamics into physical on-chip components and delay specifications. Initial modelling experiments demonstrate the ability of the processor to support real-time neural processing using 2 ditTerent neural models. The complete system is therefore an environment able, within a wide range of model characteristics, to model real-time dynamic neural network behaviour on dedicated hardware.