FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks

Authors:
David Thomas;Wayne Luk
Affiliations:
-;-
Venue:
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Year:
2009

Citing 0
Cited 8

An efficient, high-throughput adaptive NoC router for large scale spiking neural network hardware implementations

ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Hardware spiking neural network prototyping and application

Genetic Programming and Evolvable Machines
2011 Special Issue: Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware

Neural Networks
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Neural Networks
Evolving advanced neural networks on run-time reconfigurable digital hardware platform

Proceedings of the 3rd International Workshop on Adaptive Self-Tuning Computing Systems
Accelerators for biologically-inspired attention and recognition

Proceedings of the 50th Annual Design Automation Conference
2013 Special Issue: Event management for large scale event-driven digital hardware spiking neural networks

Neural Networks
FPGA simulation engine for customized construction of neural microcircuits

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Artificial neural networks are a key tool for researchers attemptingto understand and replicate the behaviour and intelligencefound in biological neural networks. Software simulations offergreat flexibility and the ability to select which aspects of biologicalnetworks to model, but are slow when operating on more complexbiologically plausible models; while dedicated hardware solutions canbe very fast, they are restricted to fixed models. This paperuses FPGAs to achieve a compromise between model complexity and simulationspeed, such that a fully-connected network of 1024 neurons,based on the biologically plausible Izhikevich spiking model,can be simulated at 100 times real-time speed. The simulatoris based on a re-usable interconnection architecture for storing synapse weights andcalculating thalamic input, which makes use of the large number of available block-RAMsand huge amounts of fine-grain parallelism. The simulatorachieves a sustained throughput of 2.26 GFlops in double-precision, and a single Virtex-5 xc5vlx330t without off-chip storage running at 133MHzis 16 times faster than a 3GHz Core2 CPU, and 1.1 times faster thana single-precision 1.2GHz 30-core GPU.