An efficient, high-throughput adaptive NoC router for large scale spiking neural network hardware implementations

Authors:
Snaider Carrillo;Jim Harkin;Liam McDaid;Sandeep Pande;Fearghal Morgan
Affiliations:
Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group, National University of Ireland, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group, National University of Ireland, Galway, Ireland
Venue:
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Year:
2010

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Abstract

Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However the use of the NoC as an interconnection fabric for large scale SNN (i.e. beyond a million neurons) demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. In this paper an adaptive NoC router architecture is proposed as a way to minimise network delay across varied traffic loads. The novelty of the proposed adaptive NoC router is twofold; firstly, its adaptive scheduler combines the fairness policy of a round-robin arbiter and a first-come first-served priority scheme to improve SNN spike packet throughput; secondly, its adaptive routing scheme (verified using simulated SNN traffic) allows the selection of different NoC router output ports to avoid traffic congestion. The paper presents the performance and synthesis results of the proposed adaptive NoC router operating within the EMBRACE architecture. Results illustrate that the high-throughput, low area and low power consumption of the adaptive NoC router make it feasible for use in large scale SNN hardware implementations.