Networks of spiking neurons: the third generation of neural network models
Transactions of the Society for Computer Simulation International - Special issue: simulation methodology in transportation systems
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
IEEE/ACM Transactions on Networking (TON)
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Real-Time Clustering of Datasets with Hardware Embedded Neuromorphic Neural Networks
HIBI '09 Proceedings of the 2009 International Workshop on High Performance Computational Systems Biology
Hardware spiking neural network prototyping and application
Genetic Programming and Evolvable Machines
NeuroPipe-Chip: A digital neuro-processor for spiking neural networks
IEEE Transactions on Neural Networks
Synaptic plasticity in spiking neural networks (SP2INN): a system approach
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
A large-scale spiking neural network accelerator for FPGA systems
ICANN'12 Proceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I
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The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65 536 neurons and 513 184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406x158 pixel image is segmented in 200 ms.