Networks of spiking neurons: the third generation of neural network models
Transactions of the Society for Computer Simulation International - Special issue: simulation methodology in transportation systems
Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control and Artificial Intelligence
Spiking Neuron Models: An Introduction
Spiking Neuron Models: An Introduction
Structure-Adaptable Neurocontrollers: A Hardware-Friendly Approach
IWANN '97 Proceedings of the International Work-Conference on Artificial and Natural Neural Networks: Biological and Artificial Computation: From Neuroscience to Technology
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Understanding the interconnection network of SpiNNaker
Proceedings of the 23rd international conference on Supercomputing
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
A gradient descent rule for spiking neurons emitting multiple spikes
Information Processing Letters - Special issue on applications of spiking neural networks
A novel approach for the implementation of large scale spiking neural networks on FPGA hardware
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Adaptive routing strategies for large scale spiking neural network hardware implementations
ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
Improving analytical models of circular concrete columns with genetic programming polynomials
Genetic Programming and Evolvable Machines
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
Neural Processing Letters
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EMBRACE has been proposed as a scalable, reconfigurable, mixed signal, embedded hardware Spiking Neural Network (SNN) device. EMBRACE, which is yet to be realised, targets the issues of area, power and scalability through the use of a low area, low power analogue neuron/synapse cell, and a digital packet-based Network on Chip (NoC) communication architecture. The paper describes the implementation and testing of EMBRACE-FPGA, an FPGA-based hardware SNN prototype. The operation of the NoC inter-neuron communication approach and its ability to support large scale, reconfigurable, highly interconnected SNNs is illustrated. The paper describes an integrated training and configuration platform and an on-chip fitness function, which supports GA-based evolution of SNN parameters. The practicalities of using the SNN development platform and SNN configuration toolset are described. The paper considers the impact of latency jitter noise introduced by the NoC router and the EMBRACE-FPGA processor-based neuron/synapse model on SNN accuracy and evolution time. Benchmark SNN applications are described and results demonstrate the evolution of high quality and robust solutions in the presence of noise. The reconfigurable EMBRACE architecture enables future investigation of adaptive hardware applications and self repair in evolvable hardware.