An empirical comparison of priority-queue and event-set implementations
Communications of the ACM
Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem
Communications of the ACM
An engineering approach to computer networking: ATM networks, the Internet, and the telephone network
Hierarchical packet fair queueing algorithms
IEEE/ACM Transactions on Networking (TON)
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
IEEE Communications Magazine
Design of a generalized priority queue manager for ATM switches
IEEE Journal on Selected Areas in Communications
Design of packet-fair queuing schedulers using a RAM-based searching engine
IEEE Journal on Selected Areas in Communications
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
Deadline-based scheduling in support of real-time data delivery
Computer Networks: The International Journal of Computer and Telecommunications Networking
Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware
ACM Transactions on Architecture and Code Optimization (TACO)
A 32GBit/s communication SoC for a waferscale neuromorphic system
Integration, the VLSI Journal
Computer Networks: The International Journal of Computer and Telecommunications Networking
Recursive design of hardware priority queues
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Computers and Electrical Engineering
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Per-flow queueing with sophisticated scheduling is one of the methods for providing advanced quality of service (QoS) guarantees. The hardest and most interesting scheduling algorithms rely on a common computational primitive, implemented via priority queues. To support such scheduling for a large number of flows at OC-192 (10 Gb/s) rates and beyond, pipelined management of the priority queue is needed. Large priority queues can be built using either calendar queues or heap data structures; heaps feature smaller silicon area than calendar queues. We present heap management algorithms that can be gracefully pipelined; they constitute modifications of the traditional ones. We discuss how to use pipelined heap managers in switches and routers and their cost-performance tradeoffs. The design can be configured to any heap size, and, using 2-port 4-wide SRAMs, it can support initiating a new operation on every clock cycle, except that an insert operation or one idle (bubble) cycle is needed between two successive delete operations. We present a pipelined heap manager implemented in synthesizable Verilog form, as a core integratable into ASICs, along with cost and performance analysis information. For a 16 K entry example in 0.13-µm CMOS technology, silicon area is below 10 mm2 (less than 8% of a typical ASIC chip) and performance is a few hundred million operations per second. We have verified our design by simulating it against three heap models of varying abstraction.