Providing guaranteed services without per flow management
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
W2F2Q: packet fair queuing in wireless packet networks
WOWMOM '00 Proceedings of the 3rd ACM international workshop on Wireless mobile multimedia
System-level modeling of a network switch SoC
Proceedings of the 15th international symposium on System Synthesis
MMNS '02 Proceedings of the 5th IFIP/IEEE International Conference on Management of Multimedia Networks and Services: Management of Multimedia on the Internet
DWDM for QoS Management in Optical Packet Switches
QoS-IP 2003 Proceedings of the Second International Workshop on Quality of Service in Multiservice IP Networks
Enhanced Weighted Round Robin Schedulers for Bandwidth Guarantees in Packet Networks
QoS-IP '01 Proceedings of the International Workshop on Quality of Service in Multiservice IP Networks
ICN '01 Proceedings of the First International Conference on Networking-Part 1
Stratified round Robin: a low complexity packet scheduler with bandwidth fairness and bounded delay
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Greedy Fair Queueing: A Goal-Oriented Strategy for Fair Real-Time Packet Scheduling
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Wavelength and time domain exploitation for QoS management in optical packet switches
Computer Networks: The International Journal of Computer and Telecommunications Networking - QoS in multiservice IP networks
Exact GPS simulation with logarithmic complexity, and its application to an optimally fair scheduler
Proceedings of the 2004 conference on Applications, technologies, architectures, and protocols for computer communications
PRO3: A Hybrid NPU Architecture
IEEE Micro
The Stratified Round Robin scheduler: design, analysis and implementation
IEEE/ACM Transactions on Networking (TON)
A buffered crossbar-based chip interconnection framework supporting quality of service
Proceedings of the 17th ACM Great Lakes symposium on VLSI
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
IEEE Transactions on Parallel and Distributed Systems
Design, Analysis and Implementation of a Novel Multiple Resource Scheduler
IEEE Transactions on Computers
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
IEEE/ACM Transactions on Networking (TON)
Exact GPS simulation and optimal fair scheduling with logarithmic complexity
IEEE/ACM Transactions on Networking (TON)
Design issues in next-generation merchant switch fabrics
IEEE/ACM Transactions on Networking (TON)
A scalable packet sorting circuit for high-speed WFQ packet scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evaluation of fair packet schedulers using a novel measure of instantaneous fairness
Computer Communications
Fair bandwidth sharing between unicast and multicast flows in best-effort networks
Computer Communications
An advanced scheduling algorithm in OFDM wireless communication systems
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
SBQ: a simple scheduler for fair bandwidth sharing between unicast and multicast flows
QofIS'02/ICQT'02 Proceedings of the 3rd international conference on quality of future internet services and internet charging and QoS technologies 2nd international conference on From QoS provisioning to QoS charging
Architecture for internal communication in multi-gigabit IP routers
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Approximation of generalized processor sharing with interleaved stratified timer wheels
IEEE/ACM Transactions on Networking (TON)
Fully hardware based WFQ architecture for high-speed QoS packet scheduling
Integration, the VLSI Journal
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part II
Contention free scheme for asymmetrical traffic load in IEEE 802.11x wireless LAN
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
Design of priority-based active queue management for a high-performance IP switch
Computers and Electrical Engineering
QFQ: efficient packet scheduling with tight guarantees
IEEE/ACM Transactions on Networking (TON)
| Hi-index | 0.08 |
The fluid generalized processor sharing (GPS) algorithm has desirable properties for integrated services networks and many packet fair queueing (PFQ) algorithms have been proposed to approximate GPS. However, there have been few high-speed implementations of PFQ algorithms that can support a large number of sessions with diverse rate requirements and at the same time maintain all the important properties of GPS. The implementation cost of a PFQ algorithm is determined by: (1) computation of the system virtual time function; (2) maintenance of the relative ordering of the packets via their timestamps (scheduling); and (3) regulation of packets based on eligibility time, in some algorithms. While most of the recently proposed PFQ algorithms reduce the complexity of computing the system virtual time function, the complexity of scheduling and traffic regulation is still a function of the number of active sessions. In addition, while reducing the algorithmic or asymptotic complexity has been the focus of most analysis, it is also important to reduce the complexity of basic operations in order for the algorithm to run at high speed. We develop techniques to reduce both types of complexities for networks of both fixed and variable size packets. Regulation and scheduling are implemented in an integrated architecture that can be viewed as logically performing sorting in two dimensions simultaneously. By using a novel grouping architecture, we are able to perform this with an algorithmic complexity independent of the number of sessions in the system at the cost of a small controllable amount of relative error. To reduce the cost of basic operations, we propose a hardware-implementation framework and several novel techniques that reduce the on-chip memory size, off-chip memory bandwidth, and off-chip access latency. The proposed implementation techniques have been incorporated into commercial ATM switch and IP router products