Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
A fully-programmable memory management system optimizing queue handling at multi gigabit rates
Proceedings of the 40th annual Design Automation Conference
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Network Systems Design with Network Processors, Agere Version
Network Systems Design with Network Processors, Agere Version
IBM PowerNP network processor: Hardware, software, and applications
IBM Journal of Research and Development
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
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The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks.