The marketplace of high-performance computing
Parallel Computing - Special Anniversary issue
Building a robust software-based router using network processors
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Small Group Multicast: A New Solution for Multicasting on the Internet
IEEE Internet Computing
Computer
C compiler design for a network processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
Considering processing cost in network simulations
MoMeTools '03 Proceedings of the ACM SIGCOMM workshop on Models, methods and tools for reproducible network research
PRO3: A Hybrid NPU Architecture
IEEE Micro
Queue Management in Network Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
FlexPath NP: a network processor concept with application-driven flexible processing paths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High-performance IPv6 forwarding algorithm for multi-core and multithreaded network processor
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
High-performance packet classification algorithm for many-core and multithreaded network processor
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A methodology for evaluating runtime support in network processors
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Software-Based Failure Detection and Recovery in Programmable Network Interfaces
IEEE Transactions on Parallel and Distributed Systems
High-performance packet classification algorithm for multithreaded IXP network processor
ACM Transactions on Embedded Computing Systems (TECS)
In-network adaptation of video streams using network processors
Advances in Multimedia
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
Journal of Systems Architecture: the EUROMICRO Journal
Improving performance of digest caches in network processors
HiPC'08 Proceedings of the 15th international conference on High performance computing
Leaping multiple headers in a single bound: wire-speed parsing using the kangaroo system
INFOCOM'10 Proceedings of the 29th conference on Information communications
Task partitioning for multi-core network processors
CC'05 Proceedings of the 14th international conference on Compiler Construction
Advanced packet segmentation and buffering algorithms in network processors
Transactions on High-Performance Embedded Architectures and Compilers IV
Instruction set architectural guidelines for embedded packet-processing engines
Journal of Systems Architecture: the EUROMICRO Journal
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Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates. As a result, more services will have to be performed at the edges, on behalf of both the core and the end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas, in the past, network equipment was based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. This paper provides an overview of the IBM PowerNPTM NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software make it well suited for a wide range of networking applications.