Error-control coding for computer systems
Error-control coding for computer systems
MIPS RISC architecture
The JPEG still picture compression standard
Communications of the ACM - Special issue on digital multimedia systems
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
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Characterizing processor architectures for programmable network interfaces
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Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 2001 conference on Applications, technologies, architectures, and protocols for computer communications
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Parallel and Distributed Systems
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IBM PowerNP network processor: Hardware, software, and applications
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Profiling and mapping of parallel workloads on network processors
Proceedings of the 2005 ACM symposium on Applied computing
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
The BSD packet filter: a new architecture for user-level packet capture
USENIX'93 Proceedings of the USENIX Winter 1993 Conference Proceedings on USENIX Winter 1993 Conference Proceedings
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Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Performance/area efficiency in chip multiprocessors with micro-caches
Proceedings of the 4th international conference on Computing frontiers
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Parallel Computing
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ACM Transactions on Embedded Computing Systems (TECS)
Modeling and analysis of core-centric network processors
ACM Transactions on Embedded Computing Systems (TECS)
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Analysis of network processing workloads
Journal of Systems Architecture: the EUROMICRO Journal
Performance analysis of multi-channel memories in mobile devices
SOC'09 Proceedings of the 11th international conference on System-on-chip
A case for multi-channel memories in video recording
Proceedings of the Conference on Design, Automation and Test in Europe
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To provide a variety of new and advanced communications services, computer networks are required to perform increasingly complex packet processing. This processing typically takes place on network routers and their associated components. An increasingly central component in router design is a chip-multiprocessor (CMP) referred to as "network processor” or NP. In addition to multiple processors, NPs have multiple forms of on-chip memory, various network and off-chip memory interfaces, and other specialized logic components such as CAMs (Content Addressable Memories). The design space for NPs (e.g., number of processors, caches, cache sizes, etc.) is large due to the diverse workload, application requirements, and system characteristics. System design constraints relate to the maximum chip area and the power consumption that are permissible while achieving defined line rates and executing required packet functions. In this paper, an analytic performance model that captures the processing performance, chip area, and power consumption for a prototypical NP is developed and used to provide quantitative insights into system design trade offs. The model, parameterized with a networking application benchmark, provides the basis for the design of a scalable, high-performance network processor and presents insights into how best to configure the numerous design elements associated with NPs.