Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Evaluation of design alternatives for a multiprocessor microprocessor
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Adapting to network and client variability via on-demand dynamic distillation
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
DPF: fast, flexible message demultiplexing using dynamic code generation
Conference proceedings on Applications, technologies, architectures, and protocols for computer communications
BPF+: exploiting global data-flow optimization in a generalized packet filter architecture
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification using tuple space search
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
SPINE: a safe programmable and integrated network environment
Proceedings of the 8th ACM SIGOPS European workshop on Support for composing distributed applications
Fast address look-up for internet routers
BC '98 Proceedings of the IFIP TC6/WG6.2 Fourth International Conference on Broadband Communications: The future of telecommunications
OS Support for General-Purpose Routers
HOTOS '99 Proceedings of the The Seventh Workshop on Hot Topics in Operating Systems
Increasing effective link bandwidth by suppressing replicated data
ATEC '98 Proceedings of the annual conference on USENIX Annual Technical Conference
Introducing new Internet services: why and how
IEEE Network: The Magazine of Global Internetworking
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
A flexible accelerator for layer 7 networking applications
Proceedings of the 39th annual Design Automation Conference
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
WRAPS Scheduling and Its Efficient Implementation on Network Processors
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
MMNS '02 Proceedings of the 5th IFIP/IEEE International Conference on Management of Multimedia Networks and Services: Management of Multimedia on the Internet
Design Tradeoffs for Embedded Network Processors
ARCS '02 Proceedings of the International Conference on Architecture of Computing Systems: Trends in Network and Pervasive Computing
Network processor requirements and benchmarking
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Fundamental architectural considerations for network processors
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Spinach: a liberty-based simulator for programmable network interface architectures
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Overcoming the memory wall in packet processing: hammers or ladders?
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
Evaluating Network Processors using NetBench
ACM Transactions on Embedded Computing Systems (TECS)
Achieving structural and composable modeling of complex systems
International Journal of Parallel Programming - Special issue: The next generation software program
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Report from the clean slate network research post-sigcomm 2006 workshop
ACM SIGCOMM Computer Communication Review
Reconciling performance and programmability in networking systems
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
Serviter: A service-oriented programmable network platform for shared infrastructure
Computer Communications
Analysis of network processing workloads
Journal of Systems Architecture: the EUROMICRO Journal
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Analysis of a reconfigurable network processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Architectural enhancements for network congestion control applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Next generation embedded processor architecture for personal information devices
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
NetSlices: scalable multi-core packet processing in user-space
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
NP-SARC: Scalable network processing in the SARC multi-core FPGA platform
Journal of Systems Architecture: the EUROMICRO Journal
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The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the crossing points, the nodes of the network, where data traffic is intercepted or forwarded. As a result, there has been tremendous interest in speeding those nodes, making the equipment run faster by means of specialized chips to handle data trafficking. The Network Processor is the blanket name thrown over such chips in their varied forms. To date, no performance data exist to aid in the decision of what processor architecture to use in next generation network processor. Our goal is to remedy this situation. In this study, we characterize both the application workloads that network processors need to support as well as emerging applications that we anticipate may be supported in the future. Then, we consider the performance of three sample benchmarks drawn from these workloads on several state-of-the-art processor architectures, including: an aggressive, out-of-order, speculative super-scalar processor, a fine-grained multithreaded processor, a single chip multiprocessor, and a simultaneous multithreaded processor (SMT). The network interface environment is simulated in detail, and our results indicate that SMT is the architecture best suited to this environment.