On the effectiveness of flow aggregation in improving instruction reuse in network processing applications

  • Authors:

  • G. Surendra;S. Banerjee;S. K. Nandy

  • Affiliations:

  • CAD Laboratory, Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India 560012;CAD Laboratory, Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India 560012;CAD Laboratory, Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India 560012

  • Venue:
  • International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
  • Year:
  • 2003

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Abstract

Instruction Reuse is a microarchitectural technique that exploits dynamic instruction repetition to remove redundant computations at run-time. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications and attempt to answer the following questions: (1) How much of instruction repetition can be reused in packet processing applications?, (2) Can the temporal locality of network traffic be exploited to reduce interference in the Reuse Buffer and improve reuse? and (3) What is the effect of reuse on microarchitectural features such as resource contention and memory accesses? We use an execution driven simulation methodology to evaluate instruction reuse and find that for the benchmarks considered, 1 to 50% of the dynamic instructions are reused yielding performance improvement between 1 and 20%. To further improve reuse, a flow aggregation scheme as well as an architecture for exploiting the same is proposed. This scheme is mostly applicable to header processing applications and exploits temporal locality in packet data to uncover higher reuse. As a side effect, instruction reuse reduces memory traffic and improves performance.