Proceedings of the seventeenth ACM symposium on Operating systems principles
Characterizing processor architectures for programmable network interfaces
Proceedings of the 14th international conference on Supercomputing
ACM Transactions on Computer Systems (TOCS)
Scheduling computations on a software-based router
Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Programming language optimizations for modular router configurations
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Lightweight Thread Tunnelling in Network Applications
IWAN '02 Proceedings of the IFIP-TC6 4th International Working Conference on Active Networks
Implementation and evaluation of a QoS-capable cluster-based IP router
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
XORP: an open platform for network research
ACM SIGCOMM Computer Communication Review
Building extensible routers using network processors: Research Articles
Software—Practice & Experience
Lightweight thread tunnelling in network applications
Computer Networks: The International Journal of Computer and Telecommunications Networking - Active networks
ATEC '00 Proceedings of the annual conference on USENIX Annual Technical Conference
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow
| Hi-index | 0.00 |
This paper argues that there is a need for routers to move from being closed, special-purpose network devices to being open, general-purpose computing/communication systems. The central challenge in making this shift is to simultaneously support increasing complex forwarding logic and high performance, while using commercial hardware components and open operating systems. This paper introduces the hardware and software architecture for such a general-purpose router. The architecture includes two key innovations. First, it better integrates the router's switching capacity and compute cycles. We expect this to result in significantly better scaling properties, and an order of magnitude improvement in performance for packets that require only minimum processing cycles. Second, the architecture supports a hierarchy of forwarding paths, ranging from fast/fixed paths implemented entirely in hardware to slow/programmable paths implemented entirely in software, but also including intermediate paths that exploit the improved integration of cycles and switching.