Building extensible routers using network processors: Research Articles

  • Authors:
  • Nadia Shalaby;Andy Bavier;Yitzchak Gottlieb;Scott Karlin;Larry Peterson;Xiaohu Qie;Tammo Spalink;Mike Wawrzoniak

  • Affiliations:
  • Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.;Department of Computer Science, Princeton University, Princeton, NJ 08544, U.S.A.

  • Venue:
  • Software—Practice & Experience
  • Year:
  • 2005

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Abstract

This paper describes our effort to build extensible routers using a combination of general-purpose and network processors. We emphasize five overriding challenges that dictate our design decisions: (1) optimal resource allocation; (2) efficient but flexible scheduling of the CPU; (3) maintaining overall router robustness; (4) maximizing router performance; and (5) providing sufficient extensibility to enable the injection of new functionality into the router. We adopt a hierarchical architecture, in which packet flows traverse a range of processing/forwarding paths, thereby partitioning hardware and software in concert. This paper both presents the architecture, and describes our experiences implementing the architecture and addressing the five design challenges in a prototype built from Intel IXP 1200 and a Pentium. Copyright © 2005 John Wiley & Sons, Ltd.