Cluster miss prediction with prefetch on miss for embedded CPU instruction caches
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Building extensible routers using network processors: Research Articles
Software—Practice & Experience
Considering network context for efficient simulation of highly parallel network processors
ICCNMC'05 Proceedings of the Third international conference on Networking and Mobile Computing
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In response to the continuous growth in network bandwidth and application requirements, specialized chips called network processors have been built to deliver high performance and flexibility at moderate cost. Network processors often employ parallelism to achieve this high performance/cost ratio. However, the same parallelism can also make the behavior of the software difficult to understand. When applications need to maintain reliable performance under heavy load, seemingly unrelated code fragments can interact with each other unexpectedly because of hardware resource contention, thereby impacting performance. To help software designers deal with this problem, we propose using software simulation to compare the impact of different design choices on performance. We show that it is possible to use relatively simple models, yet still extract information that aids in performance tuning the system.