Characterizing processor architectures for programmable network interfaces
Proceedings of the 14th international conference on Supercomputing
Building a robust software-based router using network processors
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Distributed Shared Memory: Concepts and Systems
IEEE Parallel & Distributed Technology: Systems & Technology
ICMCS '99 Proceedings of the IEEE International Conference on Multimedia Computing and Systems - Volume 2
C compiler design for a network processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NPCryptBench: a cryptographic benchmark suite for network processors
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
A folded pipeline network processor architecture for 100 Gbit/s networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Pricing and unresponsive flows purging for global rate enhancement
Journal of Electrical and Computer Engineering
Hermes: an integrated CPU/GPU microarchitecture for IP routing
Proceedings of the 48th Design Automation Conference
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Network processors (NPs) are programmable devices with special architectural features that are optimized to perform packet-processing functions. They have emerged to cope with the ever-changing networking applications that are becoming increasingly complex. NPs are expected to become the silicon core of network equipments that require a high degree of flexibility to support evolving network services at extraordinary performance with high packet rates. In this paper, we present and examine various NP architectural aspects. We describe and compare NP design characteristics and analyze their implications on the ease of programming.