Architectural implications of cache coherence protocols with network applications on chip multiprocessors

  • Authors:

  • Kyueun Yi;Jean-Luc Gaudiot

  • Affiliations:

  • Department of Electrical Engineering and Computer Science, University of California, Irvine, CA;Department of Electrical Engineering and Computer Science, University of California, Irvine, CA

  • Venue:
  • NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
  • Year:
  • 2007

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Abstract

Network processors are specialized integrated circuits used to process packets in such network equipment as core routers, edge routers, and access routers. As predicted by Gilder's law, Internet traffic has doubled each year since 1997 and this trend is showing no signs of abating. Since all emerging network applications which require deep packet classification and security-related processing should be run at line rates and since network speed and network applications complexity continue increasing, future network processors should simultaneously meet two requirements: high performance and high programmability. Single processor performance will not be sufficient to support the requirements which will be imposed on future network processors. In this paper, we consider the CMP model as the baseline architecture of future network processors. We investigate the architectural implications of cache coherence protocols with network workloads on CMPs. Our results show that the token protocol which uses the tokens to control read/write permission of shared data blocks shows better performance than the directory protocol by a factor of 13.4%.