Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
VLSI array processors
VLSI architectures for string matching and pattern matching
Pattern Recognition
Hardware Algorithms for Determining Similarity Between two Strings
IEEE Transactions on Computers
Performance and Architectural Issues for String Matching
IEEE Transactions on Computers
Optimization of Computation Time for Systolic Arrays
IEEE Transactions on Computers
An introduction to parallel algorithms
An introduction to parallel algorithms
Parallel string matching with variable length don't cares
Journal of Parallel and Distributed Computing
Faster parallel string matching via larger deterministic samples
Journal of Algorithms
String searching algorithms
Powerlist: a structure for parallel recursion
ACM Transactions on Programming Languages and Systems (TOPLAS)
A constant-time optimal parallel string-matching algorithm
Journal of the ACM (JACM)
O(1)-time parallel string-matching algorithm with VLDCs
Pattern Recognition Letters
Mapping 3-D IIR digital filter onto systolic arrays
Multidimensional Systems and Signal Processing
Constant-Time Randomized Parallel String Matching
SIAM Journal on Computing
Experiments on string matching in memory structures
Software—Practice & Experience
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CASM: A VLSI Chip for Approximate String Matching
IEEE Transactions on Pattern Analysis and Machine Intelligence
Derivation of a parallel string matching algorithm
Information Processing Letters
Design of special-purpose VLSI chips: Example and opinions
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
A fast string search algorithm for deep packet classification
Computer Communications
ClassiPl: an architecture for fast and flexible packet classification
IEEE Network: The Magazine of Global Internetworking
Search engine implications for network processor efficiency
IEEE Network: The Magazine of Global Internetworking
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
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This paper presents a systematic technique for expressing a string search algorithm as a regular iterative expression to explore all possible processor arrays for deep packet classification. The computation domain of the algorithm is obtained and three affine scheduling functions are presented. The technique allows some of the algorithm variables to be pipelined while others are broadcast over system-wide buses. Nine possible processor array structures are obtained and analyzed in terms of speed, area, power, and I/O timing requirements. Time complexities are derived analytically and through extensive numerical simulations. The proposed designs exhibit optimum speed and area complexities. The processor arrays are compared with previously derived processor arrays for the string matching problem.