A fast string searching algorithm
Communications of the ACM
Introduction to VLSI Systems
Systolic (VLSI) arrays for relational database operations
SIGMOD '80 Proceedings of the 1980 ACM SIGMOD international conference on Management of data
Architecture of the PSC-a programmable systolic chip
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Use of VLSI in algebraic computation: Some suggestions
SYMSAC '81 Proceedings of the fourth ACM symposium on Symbolic and algebraic computation
The digital divide of computing
Proceedings of the 1st conference on Computing frontiers
Processor Array Architectures for Deep Packet Classification
IEEE Transactions on Parallel and Distributed Systems
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This paper identifies important steps in the design of a special purpose VLSI chip, and argues that the most crucial step is the design of the underlying algorithm. Because the algorithm determines the degree of parallelism and pipelining that is possible, it largely determines the performance of the chip. Furthermore, if the underlying algorithm has the right properties such as modularity and regularity, then the rest of the design should be routine and thus take little effort. These claims are supported by a concrete example—the design of an efficient pattern matching chip, which has been fabricated for testing.