Processor Array Architectures for Deep Packet Classification
IEEE Transactions on Parallel and Distributed Systems
A fast string search algorithm for deep packet classification
Computer Communications
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Network processors are programmable devices with special architectural features that are optimized to perform packet forwarding decisions. Those decisions are often based on data accessed from various table structures. Access to these structures typically requires one of several search methods, each of which consists of multiple individual memory accesses, leading to significant latency to complete the process. One of the architectural features of network processors is multithreading of each processing element in order to hide the effects of these long latency searches. Hardware search engines can significantly reduce the latency of such searches, and are shown to have a significant impact on the number of threads required in each processing element.