Architectural impact of stateful networking applications
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
The impact of traffic aggregation on the memory performance of networking applications
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
NPCryptBench: a cryptographic benchmark suite for network processors
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
The impact of traffic aggregation on the memory performance of networking applications
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Journal of Systems Architecture: the EUROMICRO Journal
Analysis of network processing workloads
Journal of Systems Architecture: the EUROMICRO Journal
Hardware acceleration for media/transaction applications in network processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Parallel and Distributed Computing
Workload characterization of stateful networking applications
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
The case for hardware transactional memory in software packet processing
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Architectural enhancements for network congestion control applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving latency tolerance of network processors through simultaneous multithreading
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
Instruction set architectural guidelines for embedded packet-processing engines
Journal of Systems Architecture: the EUROMICRO Journal
Efficient traffic aware power management in multicore communications processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
High-performance hardware monitors to protect network processors from data plane attacks
Proceedings of the 50th Annual Design Automation Conference
Asymmetric scaling on network packet processors in the dark silicon era
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Modern network interfaces demand highly intelligent trafficmanagement in addition to the basic requirement of wire speedpacket forwarding. Several vendors are releasing network processorsin order to handle these demands. Network workloads can beclassified into data plane and control plane workloads, howevermost network processors are optimized for data plane. Also,existing benchmark suites for network processors primarily containdata plane workloads, which perform packet processing for aforwarding function. In this paper, we present a set of benchmarks,called NpBench, targeted towards control plane (e.g., trafficmanagement, quality of service, etc.) as well as data planeworkloads. The characteristics of NpBench workloads, such asinstruction mix, parallelism, cache behavior and requiredprocessing capability per packet, are presented and compared withCommBench, an existing network processor benchmark suite [9]. Wealso discuss the architectural characteristics of the benchmarkshaving control plane functions, their implications to designingnetwork processors and the significance of Instruction LevelParallelism (ILP) in network processors.