Performance characterization of multi-thread and multi-core processors based XML application oriented networking systems

  • Authors:
  • Jason Jianxun Ding;Abdul Waheed;Jingnan Yao;Laxmi N. Bhuyan

  • Affiliations:
  • Cisco Systems, Inc., 170 W. Tasman Drive, San Jose, CA 95134, USA;Cisco Systems, Inc., 170 W. Tasman Drive, San Jose, CA 95134, USA;Cisco Systems, Inc., 170 W. Tasman Drive, San Jose, CA 95134, USA;Department of Computer Science and Engineering, University of California, Riverside, CA 92521, USA

  • Venue:
  • Journal of Parallel and Distributed Computing
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

There is a growing trend to insert application intelligence into network devices. Processors in this type of Application Oriented Networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate the performance effect of symmetric multi-processing (SMP) via (1) hardware multi-threading, (2) uni-processor to dual-processor architectures, and (3) single to dual and quad core processing, on both packet-level and XML message-level traffic. We use AON systems based on Intel Xeon processors with hyperthreading, Pentium M based dual-core processors, and Intel's dual quad-core Xeon E5335 processors. We analyze and cross-examine the SMP effect from both highlevel performance as well as processor microarchitectural perspectives. The evaluation results will not only provide insight to microprocessor designers, but also help system architects of AON types of device to select the right processors.