Shared memory multiprocessor architectures for software IP routers

Authors:
Y. Luo;Laxmi Narayan Bhuyan;X. Chen
Affiliations:
Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA;-;-
Venue:
IEEE Transactions on Parallel and Distributed Systems
Year:
2003

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Abstract

We propose new shared memory multiprocessor architectures and evaluate their performance for future Internet protocol (IP) routers based on symmetric multiprocessor (SMP) and cache coherent nonuniform memory access (CC-NUMA) paradigms. We also propose a benchmark application suite, RouterBench, which consists of four categories of applications representing key functions on the time-critical path of packet processing in routers. An execution driven simulation environment is created to evaluate SMP and CC-NUMA router architectures using this RouterBench. The execution driven simulation can produce accurate cycle-level execution time prediction and reveal the impact of various architectural parameters on the performance of routers. We port the FUNET trace and its routing table for use in our experiments. We find that the CC-NUMA architecture provides an excellent scalability for design of high-performance IP routers. Results also show that the CC-NUMA architecture can sustain good lookup performance, even at a high frequency of route updates.