Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
Random early detection gateways for congestion avoidance
IEEE/ACM Transactions on Networking (TON)
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Efficient fair queueing algorithms for packet-switched networks
IEEE/ACM Transactions on Networking (TON)
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A Parallel IP-Address Forwarding Approach Based on Partitioned Lookup Table Techniques
LCN '04 Proceedings of the 29th Annual IEEE International Conference on Local Computer Networks
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
Architectural enhancements for network congestion control applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issues and trends in router design
IEEE Communications Magazine
MPLS: the magic behind the myths [multiprotocol label switching]
IEEE Communications Magazine
Technologies and building blocks for fast packet forwarding
IEEE Communications Magazine
IEEE Network: The Magazine of Global Internetworking
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
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As the network environment is rapidly changing, network interfaces demand highly intelligent traffic management (on control plane) in addition to the basic requirement of wire speed packet forwarding (on data plane). Several vendors are releasing various network processors (NPS) in order to handle these demands, but they are optimized for throughputs mostly in data plane. As demands for control plane applications (e.g., quality of service) grow, efficient control plane processing will become increasingly important to good performance of network interface. In this paper, we explore acceleration techniques to improve the performance of control plane network applications. Three applications including media transcoding and transaction applications are analyzed in detail. The result of workload characterization shows that wide-issue configuration shows early saturation in performance, and there is no common bottleneck among applications based on sensitivity analysis. Therefore, we study to get each application have its own hardware acceleration module in order to accomplish the required throughput on OC-768 or higher. Our approach includes array style accelerator for media transcoding applications and partitioned lookup mechanism for lookup-table-related applications. Performance analysis of the proposed techniques shows significant improvement over the baseline configuration. Such hardware accelerators provide large packet-level parallelism proportional to the number of processing elements added. Our analyses of the proposed techniques suggest future directions for the design of high-performance NPs.