Network processor requirements and benchmarking
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Efficient use of memory bandwidth to improve network processor throughput
Proceedings of the 30th annual international symposium on Computer architecture
IBM Journal of Research and Development
Efficient Field P ocessing Cores in an Innovative Protocol Processo System-on-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
High speed routers design using reconfigurable technology
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
High-speed routers design using data stream distributor unit
Journal of Network and Computer Applications - Special issue: Network and information security: A computational intelligence approach
A lookup algorithm based on multiple tables for high-speed routers
Journal of High Speed Networks
Bridging undergraduate learning and research in software and hardware
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
Analysis and evaluation of a multiple gateway traffic-distribution scheme for gateway clusters
Computer Communications
Hardware acceleration for media/transaction applications in network processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thread allocation in CMP-based multithreaded network processors
Parallel Computing
Routing to support communication in dependable networks
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
Power-Aware Parallel Forwarding: An Optimization Study
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Optimizing packet accesses for a domain specific language on network processors
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
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We provide a review of the state of the art and the future of packet processing and switching. The industry's response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrow's switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance