Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
Random early detection gateways for congestion avoidance
IEEE/ACM Transactions on Networking (TON)
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Efficient fair queueing algorithms for packet-switched networks
IEEE/ACM Transactions on Networking (TON)
Characterizing processor architectures for programmable network interfaces
Proceedings of the 14th international conference on Supercomputing
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Network Processor Design: Issues and Practices
Network Processor Design: Issues and Practices
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements
IEEE Transactions on Computers
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Architectural Support for Accelerating Congestion Control Applications in Network Processors
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
IEEE Network: The Magazine of Global Internetworking
Hardware acceleration for media/transaction applications in network processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatica (Journal of IFAC)
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Complex network protocols and various network services require significant processing capability for modern network applications. One of the important features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications--scheduling and queue management algorithms, and we propose application-specific acceleration techniques that use instruction-level parallelism (ILP) and packet-level parallelism (PLP) in these applications. From the PLP perspective, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, a large number of processing elements (PEs) and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. A 32-PE enhancement yields 24 × speedup for weighted fair queueing (WFQ) and 27 × speedup for random early detection (RED). For ILP, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10%-12% improvement in performance for instruction set enhancements. As the performance of general-purpose processors rapidly increases, defining architectural extensions (e.g., multi-media extensions (MMX) as in multimedia applications) for general-purpose processors could be an alternative solution for a wide range of network applications.