Asymmetric scaling on network packet processors in the dark silicon era

  • Authors:

  • Sourav Roy;Xiaomin Lu;Edmund Gieske;Peng Yang;Jim Holt

  • Affiliations:

  • Freescale Semiconductor Inc., Noida, India;Freescale Semiconductor Inc., Austin, USA;Freescale Semiconductor Inc., Austin, USA;Freescale Semiconductor Inc., Austin, USA;Freescale Semiconductor Inc/ MIT Computer Science and Artificial Intelligence Laboratory, Austin, USA

  • Venue:
  • ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
  • Year:
  • 2013

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Abstract

This paper introduces a new architectural technique called asymmetric scaling on heterogeneous multi-core network processor architectures to mitigate the problem of dark silicon in future process technologies. In asymmetric scaling, the number of low power cores is increased at a higher rate than the number of high performance cores over process generations. Using an analytical model we show that coupled with fixed voltage-frequency scaling, asymmetric scaling can maintain the power density of the chip at the same level for several process generations, while increasing computational capabilities according to Dennardian scaling. Asymmetric scaling aligns nicely with the application characteristics on a network packet processor. To illustrate the concept, we discuss the Layerscape network processor architecture that incorporates a general purpose layer of high performance cores with an accelerated packet processing layer of low power cores. We discuss several techniques that can be applied to reduce the power density of low power cores. Using a representative packet forwarding workload, we show that shallow-pipeline, dual-issue, in-order cores with appropriate hardware acceleration and limited on-chip memory are a good choice for the low power processor layer.