Heterogeneous Chip Multiprocessors

Authors:
Rakesh Kumar;Dean M. Tullsen;Norman P. Jouppi;Parthasarathy Ranganathan
Affiliations:
University of California, San Diego;University of California, San Diego;HP Labs;HP Labs
Venue:
Computer
Year:
2005

Citing 12
Cited 74

The case for a single-chip multiprocessor

Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Validity of the single processor approach to achieving large scale computing capabilities

Readings in computer architecture
Piranha: a scalable architecture based on single-chip multiprocessing

Proceedings of the 27th annual international symposium on Computer architecture
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Proceedings of the 31st annual international symposium on Computer architecture
Best of Both Latency and Throughput

ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Conjoined-Core Chip Multiprocessing

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Enterprise IT Trends and Implications for Architecture Research

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Scheduling for heterogeneous processors in server systems

Proceedings of the 2nd conference on Computing frontiers
Mitigating Amdahl's Law through EPI Throttling

Proceedings of the 32nd annual international symposium on Computer Architecture
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Proceedings of the 32nd annual international symposium on Computer Architecture
The Impact of Performance Asymmetry in Emerging Multicore Architectures

Proceedings of the 32nd annual international symposium on Computer Architecture

Heterogeneous multiprocessor implementations for JPEG:: a case study

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Fairness and Throughput in Switch on Event Multithreading

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
QoS policies and architecture for cache/memory in CMP platforms

Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Microprocessors in the era of terascale integration

Proceedings of the conference on Design, automation and test in Europe
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC

SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Isolation in Commodity Multicore Processors

Computer
Efficient cycle-accurate simulation of the UltraSPARC III CPU

ACSC '07 Proceedings of the thirtieth Australasian conference on Computer science - Volume 62
Fairness enforcement in switch on event multithreading

ACM Transactions on Architecture and Code Optimization (TACO)
Design methodology for pipelined heterogeneous multiprocessor system

Proceedings of the 44th annual Design Automation Conference
Interrupt modeling for efficient high-level scheduler design space exploration

ACM Transactions on Design Automation of Electronic Systems (TODAES)
VEBoC: variation and error-aware design for billions of devices on a chip

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient operating system scheduling for performance-asymmetric multi-core architectures

Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Architectural exploration of heterogeneous multiprocessor systems for JPEG

International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Predictive thread-to-core assignment on a heterogeneous multi-core processor

Proceedings of the 4th workshop on Programming languages and operating systems
Many-core design from a thermal perspective

Proceedings of the 45th annual Design Automation Conference
A stream chip-multiprocessor for bioinformatics

ACM SIGARCH Computer Architecture News
A Bridging Model for Multi-core Computing

ESA '08 Proceedings of the 16th annual European symposium on Algorithms
On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures

Microprocessors & Microsystems
Dynamic tuning of configurable architectures: the AWW online algorithm

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Dynamic power management framework for multi-core portable embedded system

IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Accelerating critical section execution with asymmetric multi-core architectures

Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Scaling the bandwidth wall: challenges in and avenues for CMP scaling

Proceedings of the 36th annual international symposium on Computer architecture
Phase-guided thread-to-core assignment for improved utilization of performance-asymmetric multi-core processors

IWMSE '09 Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering
Mapping stream programs onto heterogeneous multiprocessor systems

CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A case for integrated processor-cache partitioning in chip multiprocessors

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Reducing peak power with a table-driven adaptive processor core

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A case study on dynamic kernel adaptation in a component-based infectious disease simulator

Proceedings of the 2009 Workshop on Component-Based High Performance Computing
Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

Journal of Signal Processing Systems
Dynamic slack allocation algorithms for energy minimization on parallel machines

Journal of Parallel and Distributed Computing
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Proceedings of the 7th ACM international conference on Computing frontiers
Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations

Proceedings of the 24th ACM International Conference on Supercomputing
Area-efficient floorplans and interconnects for homogeneous multi-core architectures

International Journal of High Performance Systems Architecture
PetaBricks

XRDS: Crossroads, The ACM Magazine for Students - The Changing Face of Programming
Twin peaks: a software platform for heterogeneous computing on general-purpose and graphics processors

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Energy minimization for real-time systems with non-convex and discrete operation modes

Proceedings of the Conference on Design, Automation and Test in Europe
A bridging model for multi-core computing

Journal of Computer and System Sciences
Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Regularity-constrained floorplanning for multi-core processors

Proceedings of the 2011 international symposium on Physical design
A static task partitioning approach for heterogeneous systems using OpenCL

CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
A case for heterogeneous on-chip interconnects for CMPs

Proceedings of the 38th annual international symposium on Computer architecture
NoC frequency scaling with flexible-pipeline routers

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
L2-Cache hierarchical organizations for multi-core architectures

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Efficient and scalable scheduling for performance heterogeneous multicore systems

Journal of Parallel and Distributed Computing
Bottleneck identification and scheduling in multithreaded applications

ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Execution migration in a heterogeneous-ISA chip multiprocessor

ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
SGL: towards a bridging model for heterogeneous hierarchical platforms

International Journal of High Performance Computing and Networking
Phase-based tuning for better utilization of performance-asymmetric multicore processors

CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Compiler and runtime support for enabling reduction computations on heterogeneous systems

Concurrency and Computation: Practice & Experience
Dynamic binary rewriting and migration for shared-ISA asymmetric, multicore processors: summary

Proceedings of the 21st international symposium on High-Performance Parallel and Distributed Computing
Multicore acceleration of Discrete Event System Specification systems

Simulation
Power-efficient time-sensitive mapping in heterogeneous systems

Proceedings of the 21st international conference on Parallel architectures and compilation techniques
When less is more (LIMO):controlled parallelism forimproved efficiency

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures

The Journal of Supercomputing
An effective design of master-slave operating system architecture for multiprocessor embedded systems

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Synchronization mechanisms on modern multi-core architectures

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A hybrid heuristic-genetic algorithm for task scheduling in heterogeneous multi-core system

ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Efficient task scheduling for hard real-time tasks in asymmetric multicore processors

ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Exploring hardware overprovisioning in power-constrained, high performance computing

Proceedings of the 27th international ACM conference on International conference on supercomputing
Using DVFS and task scheduling algorithms for a hard real-time heterogeneous multicore processor environment

Proceedings of the 2013 workshop on Energy efficient high performance parallel and distributed computing
Importance of single-core performance in the multicore era

ACSC '12 Proceedings of the Thirty-fifth Australasian Computer Science Conference - Volume 122
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine

Proceedings of the 50th Annual Design Automation Conference
A shared matrix unit for a chip multi-core processor

Journal of Parallel and Distributed Computing
Modeling the effects of DFS on power consumption in hybrid chip multiprocessors

E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
Asymmetric scaling on network packet processors in the dark silicon era

ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
The sharing architecture: sub-core configurability for IaaS clouds

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Easy, fast, and energy-efficient object detection on heterogeneous on-chip architectures

ACM Transactions on Architecture and Code Optimization (TACO)
Fast and accurate power estimation method based on a PMU counter

Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
Regularity-constrained floorplanning for multi-core processors

Integration, the VLSI Journal
Analytical modeling of energy efficiency in heterogeneous processors

Computers and Electrical Engineering
A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

Journal of Parallel and Distributed Computing
Adaptive workload-aware task scheduling for single-ISA asymmetric multicore architectures

ACM Transactions on Architecture and Code Optimization (TACO)
Boosting CUDA Applications with CPU---GPU Hybrid Computing

International Journal of Parallel Programming

Quantified Score

Hi-index	4.10

Visualization

Abstract

Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a wider spectrum of system loads-from low to high thread parallelism-with high efficiency.