Conjoined-Core Chip Multiprocessing

  • Authors:

  • Rakesh Kumar;Norman P. Jouppi;Dean M. Tullsen

  • Affiliations:

  • University of California, San Diego;HP Labs, Palo Alto, CA;University of California, San Diego

  • Venue:
  • Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2004

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Abstract

Chip Multiprocessors (CMP) and Simultaneous Multi-threading (SMT) are two approaches that have been proposed to increase processor efficiency. We believe these two approaches are two extremes of a viable spectrum. Between these two extremes, there exists a range of possible architectures, sharing varying degrees of hardware between processors or threads. This paper proposes conjoined-core chip multiprocessing - topologically feasible resource sharing between adjacent cores of a chip multiprocessor to reduce die area with minimal impact on performance and hence improving the overall computational efficiency. It investigates the possible sharing of floating-point units, crossbar ports, instruction caches, and data caches and details the area savings that each kind of sharing entails. It also shows that the negative impact on performance due to sharing is significantly less than the benefits of reduced area. Several novel techniques for intelligent sharing of the hardware resources to minimize performance degradation are presented.