Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Conjoined-Core Chip Multiprocessing
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Fast configurable-cache tuning with a unified second-level cache
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework
Proceedings of the International Symposium on Code Generation and Optimization
Fast thermal simulation for architecture level dynamic thermal management
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Wavelet-based phase classification
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Effective management of multiple configurable units using dynamic optimization
ACM Transactions on Architecture and Code Optimization (TACO)
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Clustered indexing for branch predictors
Microprocessors & Microsystems
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
A self-tuning configurable cache
Proceedings of the 44th annual Design Automation Conference
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A fast and generic hybrid simulation approach using C virtual machine
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Automatic analysis of speedup of MPI applications
Proceedings of the 22nd annual international conference on Supercomputing
Multiprocessor performance estimation using hybrid simulation
Proceedings of the 45th annual Design Automation Conference
Multitasking workload scheduling on flexible core chip multiprocessors
ACM SIGARCH Computer Architecture News
Multitasking workload scheduling on flexible-core chip multiprocessors
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Direct address translation for virtual memory in energy-efficient embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Communication Based Proactive Link Power Management
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases
IEICE - Transactions on Information and Systems
Empirical Performance Models for Java Workloads
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
FlexDCP: a QoS framework for CMP architectures
ACM SIGOPS Operating Systems Review
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Program phase detection based dynamic control mechanisms for pipeline stage unification adoption
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Lightweight runtime control flow analysis for adaptive loop caching
Proceedings of the 20th symposium on Great lakes symposium on VLSI
MLP-aware dynamic cache partitioning
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Load balancing using dynamic cache allocation
Proceedings of the 7th ACM international conference on Computing frontiers
An utilization driven framework for energy efficient caches
HiPC'08 Proceedings of the 15th international conference on High performance computing
Clustering performance data efficiently at massive scales
Proceedings of the 24th ACM International Conference on Supercomputing
A Network Congestion-Aware Memory Controller
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Consistent runtime thermal prediction and control through workload phase detection
Proceedings of the 47th Design Automation Conference
Using compression algorithms to support the comprehension of program traces
Proceedings of the Eighth International Workshop on Dynamic Analysis
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Proceedings of the Conference on Design, Automation and Test in Europe
Distributed peak power management for many-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic estimation of performance requirements for software tasks of mobile devices
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Dynamic cache partitioning based on the MLP of cache misses
Transactions on high-performance embedded architectures and compilers III
Journal of Computer Science and Technology
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Efficient and scalable scheduling for performance heterogeneous multicore systems
Journal of Parallel and Distributed Computing
Function units sharing between neighbor cores in CMP
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
A fast MPSoC virtual prototyping for intensive signal processing applications
Microprocessors & Microsystems
Communication based proactive link power management
Transactions on High-Performance Embedded Architectures and Compilers IV
Dynamic resource tuning for flexible core chip multiprocessors
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Machine learning based performance prediction for multi-core simulation
MIWAI'11 Proceedings of the 5th international conference on Multi-Disciplinary Trends in Artificial Intelligence
Side-channel vulnerability factor: a metric for measuring information leakage
Proceedings of the 39th Annual International Symposium on Computer Architecture
Thermal prediction and adaptive control through workload phase detection
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Adaptive loop caching using lightweight runtime control flow analysis
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Exploring program phases for statistical bug localization
Proceedings of the 11th ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
On the feasibility of online malware detection with performance counters
Proceedings of the 40th Annual International Symposium on Computer Architecture
Trace based phase prediction for tightly-coupled heterogeneous cores
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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In a single second, a modern processor can execute billions of instructions and a program's behavior can change many times. Some programs change behavior drastically, switching between periods of high and low performance, yet system design and optimization typically focus on average system behavior. Instead of assuming average behavior, it is now time to model and optimize phase-based program behavior.