Bounded scheduling of process networks
Bounded scheduling of process networks
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Proceedings of the 30th annual international symposium on Computer architecture
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
RTCSA '07 Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Multiprocessor performance estimation using hybrid simulation
Proceedings of the 45th annual Design Automation Conference
Discovering and Exploiting Program Phases
IEEE Micro
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
Generative and Transformational Techniques in Software Engineering II
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiprocessor System-on-Chip (MPSoC) Technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional validation of AADL models via model transformation to SystemC with ATL
Proceedings of the 5th International Workshop on Model Based Architecting and Construction of Embedded Systems
Hi-index | 0.00 |
Due to the growing computation rates of intensive signal processing applications, using Multiprocessor System on Chip (MPSoC) becomes an incontrovertible solution to meet the functional requirements. Today, Electronic System Level (ESL) design is considered a vital premise to overcome the design complexity intrinsic in the heterogeneity of these devices. However, the development of tools at the system level is in the face of extremely challenging requirements such as the rapid system prototyping, the accurate performance estimation, and the reliable design space exploration (DSE). Focusing on the issue of ESL development tools, this paper describes an MPSoC environment design which targets the Multidimensional Intensive Signal Processing (MISP) application domain. Within this environment, we have defined first a generic execution model that supports any type of MPSoC. It can adapt to any parallel application and handle efficiently the scheduling and synchronizations at all the levels of granularity. Second, a new Virtual Processor (VP) based simulation technique is proposed for implementing the execution model. This proposal leverages the high-level specification of the system to provide a heterogeneous MPSoCs simulation without using an Instruction Set Simulator (ISS). VP-based simulation is implemented in SystemC at a timed transactional level allowing a good trade-off between high simulation speed and performance estimation accuracy. The usefulness and the effectiveness of our MPSoC environment is illustrated through two MISP applications executed on a typical MPSoC. Results show that our approach enables fast MPSoC virtual prototyping, data transfers and timing analysis, and reliable DSE for architectural optimizations.