Communications of the ACM
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Fault Injection Techniques and Tools
Computer
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Steering Object-Oriented Scientific Computations
TOOLS '97 Proceedings of the Tools-23: Technology of Object-Oriented Languages and Systems
An Environment for Dynamic Component Composition for Efficient Co-Design
Proceedings of the conference on Design, automation and test in Europe
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ArchC: A SystemC-Based Architecture Description Language
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
The OpenMP Source Code Repository
PDP '05 Proceedings of the 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing
Non-Preemptive Earliest-Deadline-First Scheduling Policy: A Performance Study
MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Exploiting TLM and object introspection for system-level simulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Combined software and hardware techniques for the design of reliable IP processors
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
A computational reflection mechanism to support platform debugging in SystemC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A real-time application design methodology for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CARH: service-oriented architecture for validating system-level designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-Accuracy Power and Performance Transaction-Level Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A LEON3 virtual platform with real spacewire interfaces for dependable space software development
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
A fast MPSoC virtual prototyping for intensive signal processing applications
Microprocessors & Microsystems
An efficient power estimation methodology for complex RISC processor-based platforms
Proceedings of the great lakes symposium on VLSI
Optimizing threads schedule alignments to expose the interference bug pattern
SSBSE'12 Proceedings of the 4th international conference on Search Based Software Engineering
A comparative evaluation of multi-objective exploration algorithms for high-level design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents Reflective Simulation Platform (ReSP), a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offers fine-grained simulation control and supports the evaluation of different hardware/ software configurations of a given application, enabling complete design space exploration. ReSP allows the evaluation of real-time applications on high-level hardware models since it provides the transparent emulation of POSIX-compliant Real-Time Operating Systems (RTOS) primitives. A number of experiments have been performed to validate ReSP and its capabilities, using a set of single- and multithreaded benchmarks, with both POSIX Threads (PThreads) and OpenMP programming styles. These experiments confirm that reflection introduces negligible (