Combined software and hardware techniques for the design of reliable IP processors

Authors:
M. Rebaudengo;L. Sterpone;M. Violante;Cristiana Bolchini;Antonio Miele;Donatella Sciuto
Affiliations:
Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Milano, Italy;Politecnico di Milano, Italy;Politecnico di Milano, Italy
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

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Abstract

In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the fault injection analysis campaign.