Optimizing threads schedule alignments to expose the interference bug pattern

  • Authors:

  • Neelesh Bhattacharya;Olfat El-Mahi;Etienne Duclos;Giovanni Beltrame;Giuliano Antoniol;Sébastien Le Digabel;Yann-Gaël Guéhéneuc

  • Affiliations:

  • Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada;Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada;Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada;Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada;Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada;GERAD and Department of Mathematics and Industrial Engineering, École Polytechnique de Montréal, Québec, Canada;Department of Computer and Software Engineering, École Polytechnique de Montréal, Québec, Canada

  • Venue:
  • SSBSE'12 Proceedings of the 4th international conference on Search Based Software Engineering
  • Year:
  • 2012

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Abstract

Managing and controlling interference conditions in multi-threaded programs has been an issue of worry for application developers for a long time. Typically, when write events from two concurrent threads to the same shared variable are not properly protected, an occurrence of the interference bug pattern could be exposed. We propose a mathematical formulation and its resolution to maximize the possibility of exposing occurrences of the interference bug pattern. We formulate and solve the issue as an optimization problem that gives us (1) the optimal position to inject a delay in the execution flow of a thread and (2) the optimal duration for this delay to align at least two different write events in a multi-threaded program. To run the injected threads and calculate the thread execution times for validating the results, we use a virtual platform modelling a perfectly parallel system. All the effects due to the operating system's scheduler or the latencies of hardware components are reduced to zero, exposing only the interactions between threads. To the best of our knowledge, no previous work has formalized the alignment of memory access events to expose occurrences of the interference bug pattern. We use three different algorithms (random, stochastic hill climbing, and simulated annealing) to solve the optimization problem and compare their performance. We carry out experiments on four small synthetic programs and three real-world applications with varying numbers of threads and read/write executions. Our results show that the possibility of exposing interference bug pattern can be significantly enhanced, and that metaheuristics (hill climbing and simulated annealing) provide much better results than a random algorithm.