Program phase detection based dynamic control mechanisms for pipeline stage unification adoption

Authors:
Jun Yao;Hajime Shimada;Yasuhiko Nakashima;Shin-ichiro Mori;Shinji Tomita
Affiliations:
Graduate School of Informatics, Kyoto University, Kyoto, Japan;Graduate School of Informatics, Kyoto University, Kyoto, Japan;Graduate School of Information Science, NAIST, Nara, Japan;Graduate School of Engineering, Fukui University, Fukui, Japan;Graduate School of Informatics, Kyoto University, Kyoto, Japan
Venue:
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Year:
2005

Citing 9
Cited 1

The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
Power considerations in the design of the Alpha 21264 microprocessor

DAC '98 Proceedings of the 35th annual Design Automation Conference
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Managing multi-configuration hardware via dynamic working set analysis

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A case for dynamic pipeline scaling

CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Optimizing pipelines for power and performance

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Pipeline stage unification: a low-energy consumption technique for future mobile processors

Proceedings of the 2003 international symposium on Low power electronics and design
Discovering and Exploiting Program Phases

IEEE Micro

Optimal pipeline depth with pipeline stage unification adoption

ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

To reduce the power consumption in mobile processors, a method called Pipeline Stage Unification (PSU) is previously proposed to work as an alternative for Dynamic Voltage Scaling (DVS). Based on PSU, we proposed two mechanisms which dynamically predict a suitable unification degree according to the knowledge of the program behaviors. Our results show that the mechanisms can achieve an average Energy Delay Product (EDP) decrease of 15.1% and 19.2%, respectively, for SPECint2000 benchmarks, compared to the processor without PSU.