A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depth

Authors:
Jun Yao;Shinobu Miwa;Hajime Shimada;Shinji Tomita
Affiliations:
Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Japan;School of Engineering, Tokyo University of Agriculture and Technology, Tokyo, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Japan;Graduate School of Informatics, Kyoto University, Kyoto, Japan and Institute for Integrated Cell-Material Sciences, Kyoto University, Kyoto, Japan
Venue:
Journal of Computer Science and Technology
Year:
2011

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Abstract

Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.