Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Noise tolerant low voltage XOR-XNOR for fast arithmetic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Catching Accurate Profiles in Hardware
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Transition Phase Classification and Prediction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
IEEE Computer Architecture Letters
Discovering and Exploiting Program Phases
IEEE Micro
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power gating with quality guarantees
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
On the power management of simultaneous multithreading processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating strategies on GPUs
ACM Transactions on Architecture and Code Optimization (TACO)
Guarded power gating in a multi-core setting
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
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Leakage power is projected to comprise approximately 50% of the processor's power for sub 65nm technologies. Much of this power is consumed in the processor's functional units. Accordingly, leakage control techniques are employed to reduce leakage in these functional units. Many of these techniques are dynamic and are based on an input sleep signal to initiate a low leakage mode. However, since most of these leakage control techniques are based on circuit level schemes, such techniques inherently lack information about the operational profile of the functional units they manage. This limitation is usually handled statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles. In this paper, the limitations of the static sleep signal generation approach are identified, and the use of a dynamic alternative that is capable of adopting the counter length to the running application is proposed. In order to assess the accuracy of the proposed dynamic sleep signal generator, the length of the sleep period following the sleep signal generation is used as a metric to identify the usefulness of utilizing the dynamic approach. Experimental results for the dynamic alternative shows up to 98% accuracy in predicting the length of the standby period compared to an average of 40 . 60% in the static case, which translates into increased leakage savings. This is achieved while consuming 360 ìW of overhead power at 1 GHz.