Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Dynamic power gating with quality guarantees
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE Computer Architecture Letters
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Power gating is an increasingly important actuation knob in chip-level dynamic power management. In a multi-core setting, a key design issue in this context, is determining the right balance of gating at the unit-level (within a core) and at the core-level. Another issue is how to architect the predictive control associated with such gating, in order to ensure maximal power savings at minimal performance loss. We use an abstract, analytical modeling framework to understand and discuss the fundamental tradeoffs in such a design. We consider plausible ranges of software/hardware control latencies and workload characteristics to understand when and where it makes sense to disable one or both of the gating mechanisms (i.e. intra- and inter-core). The overall goal of this research is to devise predictive power gating algorithms in a multi-core setting, with built-in "guard" mechanisms to prevent negative outcomes: e.g. a net increase in power consumption or an unacceptable level of performance loss.