ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Noise tolerant low voltage XOR-XNOR for fast arithmetic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Catching Accurate Profiles in Hardware
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
IBM Journal of Research and Development
Transition Phase Classification and Prediction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
IEEE Computer Architecture Letters
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Discovering and Exploiting Program Phases
IEEE Micro
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the power management of simultaneous multithreading processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic characteristics of power gating during mode transition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Power gating techniques are rapidly gaining popularity assisting the management of leakage power consumption for deep submicrometer microprocessors' functional units. Power gating is based on an input sleep signal to set the functional unit into a low leakage mode. However, power gating techniques in general inherently lack information about the utilization profile of the functional units they manage. This limitation is usually handled either statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles or dynamically by changing the number of cycles before the sleep signal is generated depending on the previous history of operation. In this paper, a comparative study between the static and dynamic approaches regarding the power-performance tradeoff will be presented. It will be shown that the dynamic sleep signal generator is capable of tracking the operation of the functional units while achieving accuracies up to 90% compared to an average of 40%-60% for the static sleep signal generator (SSSG). Additionally it saves up to 80% more leakage versus the SSSG. This study is very important in assisting circuit designers choose between both techniques depending on the power gated circuit.