Enchanced multi-threshold (MTCMOS) circuits using variable well bias

Dynamic fine-grain leakage reduction using leakage-biased bitlines

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture

Managing power and performance for System-on-Chip designs using Voltage Islands

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Understanding and minimizing ground bounce during mode transition of power gating structures

Proceedings of the 2003 international symposium on Low power electronics and design

On optimal physical synthesis of sleep transistors

Proceedings of the 2004 international symposium on Physical design

Characterization of logic circuit techniques for high leakage CMOS technologies

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Experimental measurement of a novel power gating structure with intermediate power saving mode

Proceedings of the 2004 international symposium on Low power electronics and design

Low-power circuits and technology for wireless digital systems

IBM Journal of Research and Development

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

IBM Journal of Research and Development

Review and future prospects of low-voltage RAM circuits

IBM Journal of Research and Development

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Analysis and optimization of gate leakage current of power gating circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Power Gating with Multiple Sleep Modes

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Physical design methodology of power gating circuits for standard-cell-based design

Proceedings of the 43rd annual Design Automation Conference

Ultralow-voltage, minimum-energy CMOS

IBM Journal of Research and Development - Advanced silicon technology

Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Enhanced leakage reduction techniques using intermediate strength power gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power-gating-aware high-level synthesis

Proceedings of the 13th international symposium on Low power electronics and design

A comparative study between static and dynamic sleep signal generation techniques for leakage tolerant designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A novel low-power full-adder cell for low voltage

Integration, the VLSI Journal

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

Microelectronics Journal

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Supply switching with ground collapse for low-leakage register files in 65-nm CMOS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)