MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Charge recycling in MTCMOS circuits: concept and analysis
Proceedings of the 43rd annual Design Automation Conference
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-switch routing for coarse-grain MTCMOS technologies
Proceedings of the 2009 International Conference on Computer-Aided Design
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Proceedings of the International Conference on Computer-Aided Design
Using synchronization stalls in power-aware accelerators
Proceedings of the Conference on Design, Automation and Test in Europe
Testing for SoCs with advanced static and dynamic power-management capabilities
Proceedings of the Conference on Design, Automation and Test in Europe
Flicker: a dynamically adaptive architecture for power limited multicore systems
Proceedings of the 40th Annual International Symposium on Computer Architecture
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A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 um CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.