Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
TSIC: thermal scheduling simulator for chip multiprocessors
PCI'05 Proceedings of the 10th Panhellenic conference on Advances in Informatics
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Clock gating is an effective means for reducing average power consumption. However, clock gating can exacerbate maximum cycle-to-cycle current swings, or the step-power (Ldi/dt) problem. We present a microarchitecture-level step-power simulator and demonstrate its use in exploring how design alternatives impact relative step-power levels. We show how the tool can be used to identify major sources of high microprocessor step-power events. Our experiments indicate that branch mispredictions are a major cause of high step-power occurrences. We also show that high step-power events are infrequent which suggest that architectural techniques may limit step-power at potentially low performance cost.