An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Breathing life into a paper tiger (keynote session)
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Power-aware modulo scheduling for high-performance VLIW processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A D&T Roundtable: Power Delivery and Distribution
IEEE Design & Test
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Proceedings of the 46th Annual Design Automation Conference
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Eliminating voltage emergencies via software-guided code transformations
ACM Transactions on Architecture and Code Optimization (TACO)
An event-guided approach to reducing voltage noise in processors
Proceedings of the Conference on Design, Automation and Test in Europe
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 39th Annual International Symposium on Computer Architecture
Performance boosting under reliability and power constraints
Proceedings of the International Conference on Computer-Aided Design
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
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While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.