Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical built-in current sensor for I_DDQ testing
Proceedings of the IEEE International Test Conference 2001
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
ICCQ: A Test Method for Analogue VLSI Base On Current Monitoring
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power signal processing: a new perspective for power analysis and optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Adapting to intermittent faults in multicore systems
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Proceedings of the 46th Annual Design Automation Conference
Eliminating voltage emergencies via software-guided code transformations
ACM Transactions on Architecture and Code Optimization (TACO)
An event-guided approach to reducing voltage noise in processors
Proceedings of the Conference on Design, Automation and Test in Europe
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Performance boosting under reliability and power constraints
Proceedings of the International Conference on Computer-Aided Design
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
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Inductive noise in high-performance microprocessors is a reliabilityissue caused by variations in processor current (di/dt)which are converted to supply-voltage glitches by impedances inthe power-supply network. Inductive noise has been addressed byusing decoupling capacitors to maintain low impedance in thepower supply over a wide range of frequencies. However, evenwell-designed power supplies exhibit (a few) peaks of high impedanceat resonant frequencies caused by RLC resonant loops. Previousarchitectural proposals adjust current variations bycontrolling instruction fetch and issue, trading off performanceand energy for noise reduction. However, the proposals do notconsider some conceptual issues and have implementation challenges.The issues include requiring fast response, responding tovariations that do not threaten the noise margins, or respondingto variations only at the resonant frequency while the range ofhigh impedance extends to a resonance band around the resonantfrequency. While previous schemes reduce the magnitude of variations,our proposal, called resonance tuning, changes the frequencyof current variations away from the resonance band to anon-resonant frequency to be absorbed by the power supply.Because inductive noise is a resonance problem, resonance tuningreacts only to repeated variations in the resonance band, andnot to isolated variations. Reacting after a few repetitions allowsmore time for the response and reduces unnecessary responses,decreasing performance and energy loss.