Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack

Authors:
Vijay Janapa Reddi;Meeta S. Gupta;Michael D. Smith;Gu-yeon Wei;David Brooks;Simone Campanoni
Affiliations:
Harvard University, Cambridge;Harvard University, Cambridge;Harvard University, Cambridge;Harvard University, Cambridge;Harvard University, Cambridge;Politecnico di Milano, Milano, Italy
Venue:
Proceedings of the 46th Annual Design Automation Conference
Year:
2009

Citing 20
Cited 4

Analysis and development of Java Grande benchmarks

JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
An architectural solution for the inductive noise problem due to clock-gating

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Dynamo: a transparent dynamic optimization system

PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Power-aware modulo scheduling for high-performance VLIW processors

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
IBM's S/390 G5 Microprocessor Design

IEEE Micro
A 1.3GHz fifth generation SPARC64 microprocessor

Proceedings of the 40th annual Design Automation Conference
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise

Proceedings of the 2003 international symposium on Low power electronics and design
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation

HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Adaptive incremental checkpointing for massively parallel systems

Proceedings of the 18th annual international conference on Supercomputing
Exploiting Resonant Behavior to Reduce Inductive Noise

Proceedings of the 31st annual international symposium on Computer architecture
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization

Proceedings of the 2004 international symposium on Low power electronics and design
Checkpointed Early Load Retirement

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging

Proceedings of the 32nd annual international symposium on Computer Architecture
ReStore: Symptom-Based Soft Error Detection in Microprocessors

IEEE Transactions on Dependable and Secure Computing
Ultra low-cost defect protection for microprocessor pipelines

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Towards a software approach to mitigate voltage emergencies

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A parallel dynamic compiler for CIL bytecode

ACM SIGPLAN Notices

A highly flexible, parallel virtual machine: design and experience of ILDJIT

Software—Practice & Experience
Software adaptation in quality sensitive applications to deal with hardware variability

Proceedings of the 20th symposium on Great lakes symposium on VLSI
A case for opportunistic embedded sensing in presence of hardware power variability

HotPower'10 Proceedings of the 2010 international conference on Power aware computing and systems
AppAdapt: opportunistic application adaptation in presence of hardware variation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-time software layer reschedules the program's instruction stream to prevent recurring margin crossings at the same program location. The run-time layer removes 60% of these events with minimal overhead, thereby significantly improving overall performance.