IBM's S/390 G5 Microprocessor Design

Authors:
Timothy J. Slegel;Robert M. Averill III;Mark A. Check;Bruce C. Giamei;Barry W. Krumm;Christopher A. Krygowski;Wen H. Li;John S. Liptay;John D. MacDougall;Thomas J. McPherson;Jennifer A. Navarro;Eric M. Schwarz;Kevin Shum;Charles F. Webb
Affiliations:
-;-;-;-;-;-;-;-;-;-;-;-;-;-
Venue:
IEEE Micro
Year:
1999

Citing 5
Cited 75

IBM S/390 parallel enterprise servers G3 and G4

IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
A high-frequency custom CMOS S/390 microprocessor

IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
CMOS floating-point unit for the S/390 parallel enterprise server G4

IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures

ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor

ICCD '98 Proceedings of the International Conference on Computer Design

Transient fault detection via simultaneous multithreading

Proceedings of the 27th annual international symposium on Computer architecture
Efficient checker processor design

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Transient-fault recovery using simultaneous multithreading

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Detailed design and evaluation of redundant multithreading alternatives

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Direct load: dependence-linked dataflow resolution of load address and cache coordinate

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Dual use of superscalar datapath for transient-fault detection and recovery

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A Fault Tolerant Approach to Microprocessor Design

DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Transient-fault recovery for chip multiprocessors

Proceedings of the 30th annual international symposium on Computer architecture
Address-free memory access based on program syntax correlation of loads and stores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

Proceedings of the 31st annual international symposium on Computer architecture
The IBM eServer z990 microprocessor

IBM Journal of Research and Development
Millicode in an IBM zSeries processor

IBM Journal of Research and Development
Fingerprinting: bounding soft-error detection latency and bandwidth

ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth

IEEE Micro
SWIFT: Software Implemented Fault Tolerance

Proceedings of the international symposium on Code generation and optimization
Design and Evaluation of Hybrid Fault-Detection Systems

Proceedings of the 32nd annual international symposium on Computer Architecture
Opportunistic Transient-Fault Detection

Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer

SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Truss: A Reliable, Scalable Server Architecture

IEEE Micro
Software-controlled fault tolerance

ACM Transactions on Architecture and Code Optimization (TACO)
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors

Proceedings of the 43rd annual Design Automation Conference
Self-checking instructions: reducing instruction redundancy for concurrent error detection

Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Static typing for a faulty lambda calculus

Proceedings of the eleventh ACM SIGPLAN international conference on Functional programming
SlicK: slice-based locality exploitation for efficient redundant multithreading

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback

IEEE Micro
Reunion: Complexity-Effective Multicore Redundancy

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Configurable isolation: building high availability systems with commodity multi-core processors

Proceedings of the 34th annual international symposium on Computer architecture
Dynamic prediction of architectural vulnerability from microarchitectural state

Proceedings of the 34th annual international symposium on Computer architecture
Fault-tolerant typed assembly language

Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Automatic Instruction-Level Software-Only Recovery

IEEE Micro
Transient fault prediction based on anomalies in processor events

Proceedings of the conference on Design, automation and test in Europe
Algorithm 867: QUADLOG—a package of routines for generating Gauss-related quadrature for two classes of logarithmic weight functions

ACM Transactions on Mathematical Software (TOMS)
Adapting to intermittent faults in multicore systems

Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
A modular 3d processor for flexible product design and technology migration

Proceedings of the 5th conference on Computing frontiers
Techniques for Efficient Software Checking

Languages and Compilers for Parallel Computing
Mixed-mode multicore reliability

Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Compiler-managed register file protection for energy-efficient soft error reduction

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Dynamic heterogeneity and the need for multicore virtualization

ACM SIGOPS Operating Systems Review
A compiler optimization to reduce soft errors in register files

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance

Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Compiler-assisted soft error detection under performance and energy constraints in embedded systems

ACM Transactions on Embedded Computing Systems (TECS)
AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware

SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Architecture Design for Soft Errors

Architecture Design for Soft Errors
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack

Proceedings of the 46th Annual Design Automation Conference
The S/390 G5/G6 binodal cache

IBM Journal of Research and Development
Custom S/390 G5 and G6 microprocessors

IBM Journal of Research and Development
S/390 microprocessor design

IBM Journal of Research and Development
The microarchitecture of the IBM eServer z900 processor

IBM Journal of Research and Development
Analysis of single-event effects in embedded processors for non-uniform fault tolerant design

IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Eliminating voltage emergencies via software-guided code transformations

ACM Transactions on Architecture and Code Optimization (TACO)
Replica victim caching to improve cache reliability against transient errors

International Journal of High Performance Systems Architecture
A compiler-microarchitecture hybrid approach to soft error reduction for register files

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DAFT: decoupled acyclic fault tolerance

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults

Proceedings of the Conference on Design, Automation and Test in Europe
Vision for cross-layer optimization to address the dual challenges of energy and reliability

Proceedings of the Conference on Design, Automation and Test in Europe
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

Journal of Systems Architecture: the EUROMICRO Journal
Static analysis to mitigate soft errors in register files

Proceedings of the Conference on Design, Automation and Test in Europe
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
On the exploitation of narrow-width values for improving register file reliability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors

SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
A self-checking hardware journal for a fault-tolerant processor architecture

International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Automated application of fault tolerance mechanisms in a component-based system

Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
Trade-offs in transient fault recovery schemes for redundant multithreaded processors

HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Failure data-driven selective node-level duplication to improve MTTF in high performance computing systems

HPCS'09 Proceedings of the 23rd international conference on High Performance Computing Systems and Applications
Resource-Driven optimizations for transient-fault detecting superscalar microarchitectures

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Static analysis and compiler design for idempotent processing

Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Runtime asynchronous fault tolerance via speculation

Proceedings of the Tenth International Symposium on Code Generation and Optimization
Warped-DMR: Light-weight Error Detection for GPGPU

MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory

Proceedings of the ACM International Conference on Computing Frontiers
FaulTM: error detection and recovery using hardware transactional memory

Proceedings of the Conference on Design, Automation and Test in Europe
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reli: hardware/software checkpoint and recovery scheme for embedded processors

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A dual process redundancy approach to transient fault tolerance for ccNUMA architecture

Neurocomputing

Quantified Score

Hi-index	0.00

Visualization

Abstract

The S/390 G5, the latest generation IBM mainframe system, more than doubles the performance of its predecessor. The microprocessor used in the system is a sophisticated CISC processor that features a large cache and a very high clock frequency to achieve excellent performance. We discuss the microarchitecture of the processor followed by a description of how this processor is integrated into the system. Finally, we consider the state-of-the-art reliability and availability features that make this mainframe system unique.