Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
IBM's S/390 G5 Microprocessor Design
IEEE Micro
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Computer Organization and Design
Computer Organization and Design
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
DSN '05 Proceedings of the 2005 International Conference on Dependable Systems and Networks
Compiler-guided register reliability improvement against soft errors
Proceedings of the 5th ACM international conference on Embedded software
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Cost-efficient soft error protection for embedded microprocessors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Using Register Lifetime Predictions to Protect Register Files against Soft Errors
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
A compiler optimization to reduce soft errors in register files
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A compiler-microarchitecture hybrid approach to soft error reduction for register files
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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For embedded systems where neither energy nor reliability can be easily sacrificed, we present an energy efficient soft error protection scheme for register files (RF). Unlike previous approaches, our method explicitly optimizes for energy efficiency and exploits the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme is more energy efficient than hardware schemes, this work formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 24%.